In a typical semiconductor memory, individual memory cells are coupled to bit lines running across the length of the memory array. The bit lines themselves are often coupled through decoder circuitry which permits addressing and accessing of the information stored within the memory cells. The information which is stored within the memory cells is commonly sensed using a sense amplifier coupled to pairs of bit lines within the memory. Most often, the sense amplifier circuitry includes an ordinary differential amplifier which provides the output data and its compliment. By way of example, a conventional memory employing sense amplifier circuitry is described in U.S. Pat. No. 4,926,387.
In BiCMOS memory circuits one of the problems that can arise is that an excessive reverse voltage appears across the differential pair of bipolar transistors at the input of the sense amplifier. This high reverse voltage may result during either a read or write operation wherein one bit line is at the most positive supply potential (V.sub.CC) and the complimentary bit line drops to the lowest supply potential (V.sub.SS). Excessive reverse voltage across the bipolar devices in the sense amplifier can lead to hot electron damage in these devices.
Currently, the problem of excessive reverse voltage across the sense amplifier input is commonly dealt with in one of two ways. In a first technique, the bit line is clamped with a diode, thereby preventing it from dropping too far below the positive supply potential. This solution has the disadvantage of drawing large currents through the RAM bit cell during the entire time that it is enabled. Thus, the diode clamp solution both increases power dissipation as well as hot electron damage.
An alternative approach adds a complex controller circuit designed to disable the RAM cell when it has generated enough voltage swing so that the sense amplifier is able to detect the state of the memory cell. The controller circuitry, however, must be sensitive enough so as not to damage the sense amplifier itself during the disabling process. In either case, the bit lines must be disconnected from the sense amplifier for write operations. In other words, the alternative approach of using a controller circuit to disable the RAM cell is both complex and incomplete.
As will be seen, the present invention provides a circuit which limits the swing appearing across the inputs of a sense amplifier without incurring a substantial delay or power penalty. The invention provides a simple and elegant solution to the problem of excessive reverse voltage and accommodates both read and write operations.